Villanova University

Department of Electrical and Computer Engineering

ECE 3971

Title: MP3 Project

Team Members:

Brian Allen

Zeeshan Khan

Jerry Koshy

Advisor: James Peyton-Jones

Background

The goal of our senior design project is to design and construct an MP3 Player. An MP3 player is an electronic device that can decode and play MP3 files. The MP3 format is a compression system for music. The number of bytes of a sound file is reduced without decreasing the quality of the file. The goal of the MP3 format is to compress a CD-quality song by a factor of 10 to 14 without losing the CD-quality sound. With an MP3, a 32-megabyte (MB) song on a CD condenses down to about 3 MB. MP3 is the short form for MPEG Audio Layer 3. MPEG refers to the Moving Pictures Experts Group, an organization that sets international standards for digital formats for audio and video. The Fraunhofer Institute in Germany developed the file-shrinking technology.[1] An MP3 player is a device that can store, decode and play these music files. An MP3 works by pulling a song from memory byte by byte, then the file is decoded. Next the decompressed bytes are sent through a digital-to-analog converter. Finally, the analog signal is amplified and sent to speakers or headphones.

(Refer to Appendix A, Figure 1 for a basic step-by-step process.)

Our group was motivated to work on this MP3 project because we wanted to combine all aspects of our software and hardware knowledge. Our design team consists of three computer-engineering majors and we decided as a group to develop an MP3 player. We plan to use our knowledge of the basic principles of digital signal processing and computer architecture to design the device.

Objectives

The purpose of our project is to design and physically create a portable MP3 player. The device utilizes a memory device for storing MP3 files. A computer will have the capability of interfacing to the memory device, so that files can be added, deleted, or rearranged. The decoder will take an MP3 file and convert it to an analog signal with the use of a digital-to-analog converter. After the file is converted, the signal will be amplified through an amplifier so that the sound can be heard with the use of speakers or headphones. There will be a user-interface to allow the user to switch songs, start and stop playback, and adjust the volume. An LCD will display song information for the user. The microprocessor will have the responsibility of coordinating all activities within the MP3 player. All devices will send and receive information from the processor.

(Refer to Appendix A, Figure 2 for a block diagram of the parts.)

This project permits Computer Engineers to design both the hardware and software aspects of making a device for playing MP3’s. An initial schematic of the project must be constructed. The schematic requires the knowledge of circuit design and theory. Since the MP3 player works with discrete data and must convert to the real-world analog signal, an understanding of digital and analog systems is necessary. In order to permit the devices in the system to communicate with each other, low-level programming is required. Also, software will allow the user to interface with the MP3 player. All of the designs will be tested on hardware simulation applications. After developing a successful computer-simulated prototype, we want the product to be implemented on a printed circuit board.

Specifications / Constraints

We researched various types of MP3 players before selecting the one appropriate for our design. The three categories are stand-alone, portable, and pc-based. The stand-alone MP3 player does not connect to a PC or its components, instead, it is built using other electronic parts such as a MP3 decoder, microprocessor, RAM, ROM, LCD display, power supply, and an operating system. The MP3 data is typically stored on a build-in hard drive or CD ROM interface. The portable player is similar to the stand-alone, except the power supply source is typically batteries. Also, the portable player is more compact and the memory source is lightweight. The final category is the PC-based player. This uses the computer for processing and decoding while the source of files is the computer hard drive.

After examining the three categories of players, we decided to design a portable system. The portable MP3 player provides mobility to a certain extent and it would allow for easy transport of the device for demonstration. One consideration that had to be taken was that this player is usually more expensive to construct and there is more complexity involved in scaling down the components.[2] Another factor taken in account was storage capacity. The storage device for the portable device is usually more expensive than the stand-alone device. The drawbacks of the PC-based MP3 player include larger size, more expense for the actual PC, and lack of transportability. The problem with stand-alone players is the difficulty to interface the hard disk or CD-ROM with the processor. Therefore, we decided to choose the portable MP3 player.

We performed extensive research on the components needed for the player. Different processors, decoders, and memory devices were analyzed. We looked at cost, reliability, feasibility, and dependability of the components. The different microprocessors that have been utilized for this type of hardware are PIC16C65, TMS320C31DSP, Hitachi 2357F, PIC16F877, Motorola 68V328, and others chips. A few decoders used are MAS3507D, VS1001K, and the TI DSP C5402. Finally, the source of the MP3’s can be the parallel port, CD-ROM, Hard Drive, SanDisk Multimedia Card, or Compact Flash.

We performed additional research on specific parts for our project. More specifically, we looked at several processors that can be used as the microcontroller for our MP3 player. The first chip that was focused on is the PIC16F84. Some of the notable characteristics of this processor are the size, which includes its reduced instruction set of 35 and 18 pin design. Another chip from the PIC family is the PIC16F877. It provides more I/O ports and includes 44 pins. The next chip that we took note is the Atmel AT90S8515 Chips. This family of Atmel chips is powerful and provides a highly flexible and cost effective solution to many embedded control applications. The Motorola MC68HC11, which is more complex than the PIC, was taken into consideration. The Motorola contains powerful bit-manipulation instructions and power saving stop and wait modes.

We began to decide on specific design requirements for our MP3 player. Looking at mounting technology, we had to choose a board. The Printed Circuit Board (PCB) will be used since we can easily add chips and solder components to the board. For the mounting characteristic of our chips, the Dual Inline Package (DIP) was the right choice. Most of the components that we have been researching come in the DIP format. These components will be easier to obtain and easier to place on our board. We decided to use DIP and surface mount chips on a PCB board. We must make sure that all of the components that we purchase are compatible with each other.

After researching and analyzing the different components, we decided to select the following devices. For the microprocessor, the PIC16F877 was selected The decoder will be the VS1001K. The SanDisk Multimedia Card will handle the memory functions. These are the three major components of the MP3 player. The specifications of each device are described in detail in the Proposed Approach section of the report.
Feasibility Analysis

An MP3 player is a common electronic device that can be bought in any electronic superstore. MP3 players have been constructed by numerous students at other universities with and without PHD programs in Engineering. There are many ways to develop an MP3 system by using different components for the storage element, decoding component, and central processing unit, which acts as the brain of the device. Presently there is numerous amount of documentation such as pictures of projects, circuit diagrams, and links to helpful information pertaining to MP3 players. After contacting successful groups and professional hobbyists about their projects, we concluded this is not the first MP3 player to be designed by undergraduate Computer Engineers.

Since other Computer Engineers designed successful, working projects it is important to look at the components they used. Our research shows that complexity of the circuit is less tedious with a simple interface with the source mp3 data. The mp3 storage elements used in projects are either a hard disk, cd-rom drive, or some type of flash/multimedia card. These components act as non-volatile sources where MP3 files are properly stored. The research also indicates decoders in the majority of the successful projects were MAS3507D, VS1001K, and STA013. These three decoders are able to perform the digital signaling processing aspect in order to save us valuable time in order to complete the project. The project can be done within a budget of 150 dollars assuming that we use an inexpensive processor. Processors such as the Atmel AT90S8515, PIC16F877 and PIC12C508A-04/P appear to be the least expensive chips that keep us within tolerable budget.

Hard Drive:

From our research, “a hard disk is part of a unit, often called a "disk drive," "hard drive," or “hard disk drive,” that store and provides relatively quick access to large amounts of data on an electromagnetically charged surface or set of surfaces. Today's computers typically come with a hard disk that contains several billion bytes (gigabytes) of storage.

A hard disk is really a set of stacked "disks," each of which, like phonograph records, has data recorded electromagnetically in concentric circles or "tracks" on the disk. A "head" (something like a phonograph arm but in a relatively fixed position) records (writes) or reads the information on the tracks. Two heads, one on each side of a disk, read or write the data as the disk spins. Each read or write operation requires that data be located, which is an operation called a "seek." (Data already in a disk cache, however, will be located more quickly.)

A hard disk/drive unit comes with a set rotation speed varying from 4500 to 7200 rpm. Disk access time is measured in milliseconds. Although the physical location can be identified with cylinder, track, and sector locations, these are actually mapped to a logical block address (LBA) that works with the larger address range on today's hard disks.”[3]

Below are the specifications for the Western Digital Layout Caviar 1.5 Gigabytes[4]

Figure B.1) Western Digital Layout Caviar 1.5 Gigabytes Specifications

Form	3.5"/SLIMLINE			Native	Translation
Capacity form/uniform	1624/	MB	Cylinders		3148
Seek time av./s. track	11.0/ 3.0	ms	Heads	6	16
Controller	IDE / ATA2 FAST/ENHA		Sector/track		63
Cache/Buffer KB	128 ADAPTIVE		Precompensation
Data transfer rate int.		MB/s	Landing Zone
Transfer ext. DMA2	16.600	MB/s	Bytes/Sector	512
Recording method	RLL 1/7

					operating	non-operating
Supply voltage		5/12 V	Temperature	°C	5 / 55	-40 / 60
Power: sleep	W	0.5	Humidity	%	8 / 80	5 / 95
standby	W	0.5	Altitude	Km	-0.305 / 3.048	-0.305 / 12.192
idle	W	4.3	Shock	g	10	150
seek	W		Rotation	RPM	5200
read/write	W	4.3	Acoustic	Dba	37
spin-up	W	11.2	ECC	bit	REED SOLOMON
			MTBF	h	300000
			Warranty	Month	36
Lift/Lock/Park		YES	Certificates		CSA,FCC,IEC950,TUV,UL1950

Figure B.2) Top View LAYOUT of Western Digital Layout Caviar 1.5 Gigabytes

Figure B.3) Specific Pinouts of Western Digital Layout Caviar 1.5 Gigabytes

Pros of using a hard disk:

Store hundreds of Mp3 format files
Quick access time
Durable
Been successfully used

Cons

Physical Size
Searching for data
Bulky
Logical complexity
Interface complexity

CD-ROM Drive:

A CD-ROM stands for Compact Disc, read-only-memory is an adaptation of the CD that is designed to store computer data in the form of text and graphics, as well as hi-fi stereo sound. Although the disc media and the drives of the CD and CD-ROM are, in principle, the same, there is a difference in the way data storage is organized. Two new sectors were defined, Mode 1 for storing computer data and Mode 2 for compressed audio or video/graphic data so we will use mode 2. Mode 2 uses only two layers of error detection and correction, the same as the CD-DA. Therefore, all 2,336 bytes of data behind the sync and header bytes are for user data. Although the sectors of CD-DA, CD-ROM Mode 1 and Mode 2 are the same size, the amount of data that can be stored varies considerably because of the use of sync and header bytes, error correction and detection. The Mode 2 format offers a flexible method for storing graphics and video.

The CD-ROM has Constant Linear Velocity (CLV) is the principle by which data is read from a CD-ROM. This principal states that the read head must interact with the data track at a constant rate, whether it is accessing data from the inner or outermost portions of the disc. This is affected by varying the rotation speed of the disc, from 500 rpm at the center, to 200 rpm at the outside. In a music CD, data is read sequentially, so rotation speed is not an issue. The CD-ROM, on the other hand, must read in random patterns, which necessitates constantly shifting rotation speeds. Pauses in the read function are audible, and some of the faster drives can be quite noisy because of it.[5]

Figure B.4) Acer CD-ROM drive[6]

Acer CD-656A

Price $30.00

52x max speed

Figure B.5) Specifications for the Acer CD-656A CD-ROM drive

Data Transfer Rate	8,400 KB/sec max., 33.3 MB/sec (Ultra DMA mode)
Access Time	90 ms typical
Buffer Size	128KB
Interface	E-IDE
Disk Format	CD-Audio, CD-ROM (mode 1 and mode 2), CD-ROM XA (mode 2, form 2), CD-Plus, CD-i/FMV, Video CD, PhotoCD (single & multi-sessions), I-TRAX Enhanced CD, Karaoke CD, CD-R, CD-RW
Disk Size	80 mm and 120mm
Power Requirement	DC 5V?5% 450mA typical, DC 12V?5% 650mA typical
Dimensions	5.7"(W) x 1.7"(H) x 8.3"(D)
Weight	2.0 Lbs
Firmware Update	Flash memory upgrade
Accessories	1pc User's guide 1pc Audio cable 1pc DOS device driver disk (3 1/2" floppy) 4pcs Mounting screws

Figure B.6) Interface for the Acer CD-656A CD-ROM drive

Figure B.7) Pinouts for the Acer CD-656A CD-ROM drive

Pin No.	Signal Name	Pin No.	Signal Name
1	Address Bit 0	21	Write Enable
2	Ground	22	Ground
3	Address Bit 1	23	Bus Enable
4	Ground	24	Ground
5	Not connected	25	Data Bit 0
6	Ground	26	Ground
7	Not connected	27	Data Bit 1
8	Ground	28	Ground
9	Not connected	29	Data Bit 2
10	Ground	30	Ground
11	Not connected	31	Data Bit 3
12	Ground	32	Ground
13	Interrupt	33	Data Bit 4
14	Ground	34	Ground
15	Data request For DMA	35	Data Bit 5
16	Ground	36	Ground
17	Data Acknowledge For DMA	37	Data Bit 6
18	Ground	38	Ground
19	Read Enable	39	Data Bit 7
20	Ground	40	Ground

Pros

Error correcting and CLV
Able to store 300 hundreds MP3
Cheaper then Hard drive
Ease of changing data
Slim and lightweight size of discs

Cons

· Optical interface

· Pin Interfacing with other components

· Two Modes of operation

· Bulky

· Interface complexity

· Not portable (data can be misread or skipped)

Flash devices:

Flash memory (sometimes called "flash RAM") is a type of constantly-powered nonvolatile memory that can be erased and reprogrammed in units of memory called blocks. It is a variation of electrically erasable programmable read-only memory (EEPROM) which, unlike flash memory, is erased and rewritten at the byte level, which is slower than flash memory updating. Flash memory is often used to hold control code such as the basic input/output system (BIOS) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written to in block (rather than byte) sizes, making it easy to update. On the other hand, flash memory is not useful as random access memory (RAM) because RAM needs to be addressable at the byte (not the block) level.

Flash memory gets its name because the microchip is organized so that a section of memory cells are erased in a single action or "flash." The erasure is caused by Fowler-Nordheim tunneling in which electrons pierce through a thin dielectric material to remove an electronic charge from a floating gate associated with each memory cell. Intel offers a form of flash memory that holds two bits (rather than one) in each memory cell, thus doubling the capacity of memory without a corresponding increase in price.

Flash memory is used in digital cellular phones, digital cameras, LAN switches, PC Cards for notebook computers, digital set-up boxes, embedded controllers, and other devices.[7]

Figure B.8) SanDisk Multimedia Card[8]

Multimedia Card

Price $ 24.99

Figure B.9) Specifications of Multimedia Card

Dimensions: 45.0mm x 37.0mm x 0.76mm
Operating temperature range: 0° C to +55°C
Connector pins: 22

Both cards can perform the same functions; the only difference between the two is the multimedia card uses less pins, making it easier to interface.

Figure B.10) Pinouts for the SanDisk Multimedia Card

Pros

Physically Smaller
Only 7 pins needed to operation
No other moving parts like a hard drive or CD-ROM

Cons

Data Size more limited
No type of ECC
More expensive per byte

Decoders:

The MAS 3507D is a single-chip MPEG layer 2/3 audio decoder for use in audio broadcast or memory based playback applications. Due to embedded memories,

the embedded DC/DC up-converter, and the very low power consumption, the MAS 3507D is ideally suited for portable electronics. In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have been standardized. The most sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo signals while still maintaining CD audio quality. Layer 2 (widely used in DVB, ADR, and DAB) achieves a compression of 8:1 providing CD quality. In order to achieve better audio quality at low bit rates (<64 kbit/s per audio channel), three additional sampling frequencies are provided by MPEG 2 (ISO 13818-3). The MAS 3507D decodes both layer 2 and layer 3 bit streams as defined in MPEG 1 and 2.The multichannel/multilingual capabilities defined by MPEG 2 are not supported by the MAS 3507D. An extension to the MPEG 2 layer 3 standard developed by FhG Erlangen, Germany sometimes referenced as MPEG 2.5, for extremely low bit rates at sampling frequencies of 12, 11.025, or 8 kHz is also supported bythe MAS 3507D.

This decoder has 44 pins, below is table that defines the first 8 pins for this decoder.[9]

Figure B.11) Pinouts for the MAS 3507D decoder

1 6 TE IN VSS Test Enable

2 5 POR IN VDD Reset, Active Low

3 4 I2CC IN VDD I2C Clock Line

4 3 I2CD IN/OUT VDD I2C Data Line

5 2 VDD SUPPLY X Positive Supply for Digital Parts

6 1 VSS SUPPLY X Ground Supply for Digital Parts

7 44 DCEN IN X Enable DC/DC Converter or Voltage Supervision

8 43 EOD OUT LV PIO End of DMA, Active Low

VS1001k is a single-chip solution for an MPEG layer 1, 2 and 3 audio decoder. The chip contains a high-performance low-power DSP processor core (VS DSP), working memory, 4 kBytes of program RAM and 0.5 kBytes of data RAM for user applications, serial control and input data interfaces, and a high-quality oversampling variable sample-rate stereo DAC, followed by an earphone amplifier and a ground buffer. VS1001k receives its input bit stream through a serial input bus, which it listens to as a system slave. The input stream is decoded and passed through an analog/digital hybrid volume control to an 18-bit oversampling, multi-bit, sigma-delta DAC. The decoding is controlled via a serial control bus. In addition to the basic decoding, it is possible to add application specific features, like DSP effects, to the user RAM memory. This decoder has 28 pins.[10]

Figure B.12) Pin Name Pin Type Function for the VS1001K decoder

DREQ 1 DO data request, input bus	TEST0 15 DI reserved for test, connect to DVDD
DCLK 2 DIO serial input data bus clock	TEST1 16 DIO reserved for test, do NOT connect!
SDATA 3 DI serial data input	TEST2 17 DIO reserved for test, do NOT connect!
BSYNC 4 DI byte synchronization signal	AGND1 18 PWR analog ground
DVDD1 5 PWR digital power supply	AVDD1 19 PWR analog power supply
DGND1 6 PWR digital ground	RIGHT 20 AO right channel output
XTALO 7 CLK crystal output	AGND2 21 PWR analog ground
XTALI 8 CLK crystal input	RCAP 22 AIO capacitance for reference
DVDD2 9 PWR digital power supply	AVDD2 23 PWR analog power supply
DGND2 10 PWR digital ground	LEFT 24 AO left channel output
XCS 11 DI chip select input (active low)	AGND3 25 PWR analog ground
SCLK 12 DI clock for serial bus	XRESET 26 DI active low asynchronous reset
SI 13 DI serial input	DGND3 27 PWR digital ground
SO 14 DO3 serial output	DVDD3 28 PWR digital power supply

STA013 was designed for MP3 decoders. STA013 can decode Layer III compressed streams only, because the lower layers I and II are not supported by this device.

It is particularly suitable for Multimedia application, because it can drive the data demand by a dedicated pin. This signal can be used by the system controller to synchronize the data to STA013 input port. It can work with three different standard commercial crystals, 10.00, 14.31818, and 14,7456 MHz. The device can perform both digital Volume and Tone Control, avoiding the use of the correspondent analog components on the application. The most important DAC data format (I2S, etc.) is supported.[11]

Figure B.13) Pin Name Pin Type Function for the STA013 decoder

1 29 B5 VDD_1 Supply Voltage	15 7 G4 VSS_3 Ground
2 30 B4 VSS_1 Ground	16 8 G5 VDD_3 Supply Voltage
3 31 A4 SDA I/O i2C Serial Data + Acknowledge CMOS Input Pad Buffer	17 10 F5 PVDD PLL Power
4 32 B3 SCL I I2C Serial Clock CMOS Input Pad Buffer	18 11 G6 PVSS PLL Ground
5 34 A1 SDI I Receiver Serial Data CMOS Input Pad Buffer	19 12 G7 FILT O PLL Filter Ext. Capacitor Conn.
6 36 B2 SCKR I Receiver Serial Clock CMOS Input Pad Buffer	20 13 G8 XTO O Crystal Output CMOS 4mA Output Drive
7 38 D4 BIT_EN I Bit Enable CMOSInput Pad Buffer	21 15 F7 XTI I Crystal Input (Clock Input) Specific Level Input Pad
8 40 D1 SRC_INT I Interrupt Line For S.R. Control CMOS Input Pad Buffer	22 19 E7 VSS_4 Ground
9 42 E2 SDO O Transmitter Serial Data (PCM	23 21 C8 VDD_4 Supply Voltage
10 44 F2 SCKT O Transmitter Serial Clock CMOS 4mA Output Drive	24 22 D7 TESTEN I Test Enable CMOSInput Pad Buffer
11 2 H1 LRCKT O Transmitter Left/Right Clock CMOS 4mA Output Drive	27 26 A5 VSS_5 Ground
12 3 H3 OCLK I/O Oversampling Clock for DAC CMOS Input Pad Buffer	28 27 C5 OUT_CLK/
13 5 F3 VSS_2 Ground
14 6 E4 VDD_2 Supply Voltage

Processors:

The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR RISC

architecture. By executing powerful instructions in a single clock cycle, the AT90S1200

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to

optimize power consumption versus processing speed. The AVR core combines a rich instruction set with the 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.[12]

The Hitachi H8S/2357F is a popular 16-bit microcontroller from the Hitachi H8S series. Reasons for success of this microcontroller include the large on-chip Flash and RAM memory and the large peripheral set detailed below.[13]

Figure B.14) H8S/2357F Features

· 16-bit H8S/2000 CPU – 20MHz maximum (at 5v)

· 128KB Flash (internal, single voltage supply, 16-bit single state)

· 8KB RAM (internal, 16-bit single state)

· Bus controller offering 16MB 8/16-bit external access, programmable

wait states and chip selects across 8 memory areas

· Direct Memory Access Controller (DMAC)

· Data Transfer Controller (DTC – flexible DMAC like peripheral)

· 6-channel 16-bit Timer Pulse Unit (TPU)

· Programmable Pulse Generator (PPG)

· 2 x 8-bit timer channels

· Watchdog timer

· 3 Serial Communication Interface (SCI) channels

· 8 channel 10-bit A/D converter

· 2 channel 8-bit D/A converter

· 87 I/O pins and 8 input only pins

The PIC16F877 is a powerful (200 nanosecond instruction execution) yet easy-to-program (only 35 single word instructions) CMOS FLASH-based 8-bit microcontroller packs Microchip's powerful PIC architecture into an 40- or 44-pin package and is upwards compatible with the PIC16C5X, PIC12CXXX and PIC16C7X devices. The PIC16F877 features 256 bytes of EEPROM data memory, self programming, an ICD, 8 channels of 10-bit Analog-to-Digital (A/D) converter, 2 additional timers, 2 capture/compare/PWM functions, the synchronous serial port can be configured as either 3-wire Serial Peripheral Interface (SPI™) or the 2-wire Inter-Integrated Circuit (I²C™) bus and a Universal Asynchronous Receiver Transmitter (USART). All of these features make it ideal for more advanced level A/D applications in automotive, industrial, appliances and consumer applications.[14]

Figure B.15) PIC16LF877 Features

Program Memory:		Status
	14336 (Bytes), 8192 (Words)	In Production

Specification Chart

Data Ram	Speed MHz	I/O Ports	ADC 10-bits	Serial I/O	PWM	Comp- arators	Timers	Brown Out	ICSP
368	20	33	8	USART, I²C, SPI	2	-	3+WDT	True	True

Additional Features
	256 Bytes EEPROM data memory, ICD, 25mA sink/source per I/O, Self Programming, Parallel Slave Port, 2 Capture/Compare

Low Voltage Device Option:
	PIC16LF877

Package Options
	44 PLCC(L), 44 MQFP(PQ), 40 PDIP(P), 44 TQFP(PT)

Proposed Approach

We began to decide on specific design requirements for our MP3 player. After research on the file format of MP3’s and the technology behind the devices that support these files, we began to look at different components for our MP3 player. As seen in our feasibility report, we analyzed several options for each component. We looked at the devices necessary to support memory, digital signal processing, and central processing units. We found out that our options for devices were limited. One of the main reasons for the limitation is budget. We could not exceed $150, therefore, we had to choose components that are not expensive. We also looked at compatibility between the components and our overall design.

Our overall design begins first with a step by step process that an MP3 player must take in order to play a file. A file in the MP3 format will be stored in a memory device. Then the file will be taken from the memory byte by byte. This information will be decompressed using MP3 decoding technology. While the data is being decompressed, the bytes will be sent through a digital to analog converter. After being sent through the digital to analog converter, the signal will be amplified to an audible sound. This sound may come out of a speaker or headphones. Refer to figure A.1 for the stepwise process of an MP3 player.

As we go further in depth into the MP3 player technology, we discover the components that are necessary for the project. Each component works together in order achieve the final output, which is the amplified signal, or sound, that can be heard. Figure A.2 has the necessary components of an MP3 player.

After carefully looking over our feasibility report, we were able to make decisions on the approach that we would like to take while designing our MP3 player.

Looking at mounting technology, we had to choose a board. The Printed Circuit Board (PCB) will be used since we can easily add chips and solder components to the board. For the mounting characteristic of our chips, the Dual Inline Package (DIP) was the right choice. Most of the components that we have been researching come in the DIP format. These components will be easier to obtain and easier to place on our board. We decided to use DIP and surface mount chips on a PCB board. We must make sure that all of the components that we purchase are compatible with each other.

Our ideal approach to the final design depends on the decoder. Although the main processor is the “brains” of the project, the decoder will play one of the most important parts in the final design. The decoder will take the data from the memory and perform the digital signal processing necessary to convert the MP3 file from a digital to an analog signal. The decoder that we have decided to choose is the VS1001K. There are many key features that make this decoder appealing to our design. It has a built-in DAC, therefore we do not have to purchase a separate component to handle the digital-to-analog conversions. In addition to the DAC, the decoder also has a built-in amplifier. Again, this is one less component that must be purchased and interfaced. The VS1001K is capable of serial control and data interfaces. It has 4kB of built-in RAM and the decoder can handle variable bit rates. These options and the price make the VS1001K decoder the appropriate component for our design.

The microcontroller will take the data from the storage unit and send it to the decoder. The processor will also be responsible for interfacing the user controls to the actual data and decoder. The PIC processor is the processor that we have decided to choose. The PIC16F877 chip has 44 pins and it has a small instruction set of 35. It is capable of handling serial communication. The PIC16F877 has a reduced instruction set (RISC) and it runs with a 20 MHz clock input, allowing for an instruction cycle to take 200ns. This microprocessor operates at a voltage range of 2.0V to 5.5V allowing for easy compatibility with other components. And since we have previous knowledge on the chip, we will be able to program the processor with fewer problems.

As we order our parts, we will also work on our design and schematic layouts. We are currently looking at the pin layouts of the chips. The specifications of each chip will allow us to test the component. Therefore, while we are testing our components, we will also design the layout of the circuit. We will run simulations on computer programs so that we can debug our design. If there are any mistakes in our design, we do not want to risk damaging chips. Therefore, it is important to run simulations on a computer.

Once we have determined that all of the components are working, we will test them. We will make each device perform specific operations. For our memory device, we will place data on the component, remove data, and move data. There may be other tests that we come upon as we continue to work on the project. For the decoder, we will send some data through the chip and attempt to retrieve a manipulated version of the data. Our processor will be tested to perform functions, such as math problems, retrieving and sending data, and controlling our components in our MP3 player. Sending a signal through the device will test the amplifying unit. Using an oscilloscope, we will determine if the amplifier is performing as planned. We can test the speaker unit by sending an audio signal to the device. A user interface control unit will first be designed as a computer program. We will decide what functions will be necessary for the MP3. The main functions necessary for the device are Play, Stop, Forward, and Back. We will add many more functions as time permits.

Once the devices have been tested, we can begin to put the components together. We will place components together and test them out. If they work as desired, we will add the next set of components to the overall structure. There will be considerable testing and debugging involved in our proposed approach.

We will continue to work into the summer. As we arrive back at school in the fall, we will continue to test and debug our architecture.

Tasks of Proposed Approach

Task 1 – Multimedia Card Programming (Brian)

In order to utilize the Multimedia Card (MMC), the MMC must be programmed. This will be accomplished using the Parallel Port on a PC. The program will be written in C++ and will initialize and program the MMC. This program will contain the file names of the tracks and also create a table of contents for the MMC. In the table of contents, the location of the address will be 32 bits, allocating four bytes for each MP3 file. The first address in the contents will contain the total number of tracks. On the startup, the table of contents will be stored into SRAM by the MMC. The address for the first track will be in the next memory location. The second track will be in an address location that will be plus four from the first track. Refer to Figure C.1 for a block diagram of the interfacing.

Task 2 – Memory Interfacing (Brian & Jerry)

The MMC will also need to be interfaced with the PIC microcontroller. The MMC uses a Serial Peripheral Interface (SPI) to control and transfer its data.[15] SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers. SPI-compatible interfaces range into the tens of megahertz and it is very efficient in applications that take advantage of its duplex capability, such as the communication between a coder/decoder and a digital signal processor, which consists of simultaneously sending samples in and out. SPI devices communicate using a master-slave relationship.[16] The MMC will be the slave and the microcontroller will be the master in this situation. The SPI interface between the microcontroller and the MMC will use the microcontroller hardware.[17] The synchronous serial port on the PIC can be configured as either 3-wire Serial Peripheral Interface (SPI™) or the 2-wire Inter-Integrated Circuit (I2C™) bus and a Universal Asynchronous Receiver Transmitter (USART).[18] Refer to Figure C.2 for the pin diagram of the PIC.

Task 3 – MP3 Decoder Programming and Interfacing (Zeeshan)

The MP3 decoder will also need to be interfaced with the microcontroller. This chip will use two types of serial interfaces. The first will be serial data interface (SDI), which will allow the VS1001 to receive its input bit stream through a serial input bus. The input stream is decoded and passed to an 18-bit over sampling, multi-bit, sigma-delta DAC. This decoding is controlled via a serial control bus called the serial command interface (SCI). The SCI is compatible with SPI-bus specification. In addition to basic decoding, it is possible to add application specific features, like DSP effects, to the program RAM memory of VS1001.[19] Please refer to figure C.2 for the structure of the VS1001, the Very Low power MP3 Audio Player Chip. [20]

Task 4 – Microprocessor Programming (All)

The microcontroller will need to be programmed in order to perform many different but

significant tasks. First it will need to setup the different serial interfaces, as well as the ports for the pushbuttons and display unit. Also this program for the PIC will initialize all variables, permit interrupts, and setup the reset. It will then need to initialize the MMC, by accepting data through the SPI interface and loading the table of contents into the SRAM. The microcontroller will also be responsible for initializing the Decoder and sending data to the Decoder via the SDI interface. The PIC will enable and start the decoding and begin the timer. The programming of the PIC will be extremely involved, but will be successfully completed with some professional assistance.

Task 5 – User Interface Functionality (Jerry)

The user interface and display unit will be additional features requiring some attention. The playback controls will allow the user to change and stop the current MP3 track. The controls will consist of PLAY, STOP, NEXT, and PREVIOUS. This will be constructed using pushbuttons connected to the microcontroller. The display unit will require a driver unit to control the LED and this will be accomplished via a serial interface to the microcontroller. [21] The display unit will be completed if time permits.

Task 6 – Circuit Board Construction (All)

The final task will be placing all the components on the Printed Circuit Board (PCB) will be used since we can easily add chips and solder components to the board. For the mounting characteristic of our chips, the Dual Inline Package (DIP) will be used. Most of the components that we have been researching come in the DIP format. This task will include adding the voltage source of 3.3V batteries and an oscillator to generate a signal for the Decoder chip.

Task 7 – Final Testing and Debugging (All)

Although this task will be incorporated in each of the above tasks, final testing will be done to ensure the project is completely functional. Also, this task will act as extra time to rectify any unexpected problems that rise up during the construction of the device.

Test and Evaluation Plan

As we order our parts, we will also work on our design and schematic layouts. The specifications of each chip will allow us to test the component. We will run simulations on computer programs so that we can debug our design. If there are any mistakes in our design, we do not want to risk damaging chips. Therefore, it is important to run simulations on a computer especially for the PIC processor. We will utilize the PIC development software in the labs of CEER.

There are several methods to test the modes in the VS1001k decoder, which allow the user to perform memory tests, SPI bus tests, and several different sine wave tests ranging from 250 Hz to 1500 Hz. All tests are started in a similar way: if some MP3 has been decoded, the decoding has to be finished by sending 1024 zero bytes. This ensures that the decoder is looking for the next header and will not translate the testing commands to be valid MP3 data. If no MP3 data has been decoded since the last reset, this step doesn’t have to be taken. Sending a 4-byte special command sequence starts each test. The sequences are described below. Note, that after each special command, at least 4 zeros must be transmitted for the command to take effect. [22]

Another test is the memory test. This Memory test mode is initialized by the sequence 0x4D 0xEA 0x6D 0x54. After this command (and its required 4 zeros), wait for 500000 clock cycles. The result can be read from the SPI register HDAT0, and ’one’ bits are interpreted as follows:

Bit(s)	Meaning
0	Good X ROM
1	Good Y ROM (high)
2	Good Y ROM (low)
3	Good Y RAM
4	Good X RAM
5	Good Instruction RAM (high)
6	Good Instruction RAM (low)
7	Unused

All tests are non-destructive and interrupts are disabled during testing. Thus, no user software or data is harmed by the tests. Instruction ROM cannot be tested with software. [23]

A test that is also useful is the SCI test. The SCI test is initialized by the sequence: 0x53 0x70 0xEE n, where n ¡ 48 is the register number to test. The content of the given register is read and copied to HDAT0. If the register to be tested is HDAT0, the result is copied to HDAT1. [24]

The final test for the Decoder is the Sin test. Sine test is initialized by the sequence: 0x53 0xEF 0x6E n, where n (48..119) defines the sine test to use. If we define FsIdx = (n ¡ 48)mod9 and FSin = (n ¡ 48)=9, the following tables may be used:

FsIdx	Fs
0	44100 Hz
1	48000 Hz
2	32000 Hz
3	22050 Hz
4	24000 Hz
5	16000 Hz
6	11025 Hz
7	12000 Hz
8	8000 Hz

FSin	Length of Sin
0	32.000 samples
1	16.000 samples
2	10.667 samples
3	8.000 samples
4	6.400 samples
5	5.333 samples
6	4.571 samples
7	4.000 samples

To exit the sine test, send the sequence 0x45 0x78 0x69 0x74. [25]

The LCD can be tested using an LCD emulator. The emulator mimics the real LCD and allows the users to test the code for the LCD. The pushbuttons can be easily tested using a simple circuit and seeing if the desired output is correct.

The SanDisk Multimedia Card program can be tested by attempting to store MP3 files on the MMC and determining if the MMC transfers data. Figure C.4 demonstrates how a flow chart can be used to determine if the MMC is programmed correctly.[26]

Schedule

Here is a general project schedule:

Phases:

1. Research & Component Selection

2. Preliminary Design & Ordering of Parts

3. Construction & Testing

FIGURE C.5 – Phase Schedule

Figure C.6 on the next page is a very specific Gantt Chart of the project schedule. The tasks used in the chart are similar to the proposed tasks but a few tasks have been added. These new tasks incorporate the events which lead to the project approval and initial research conducted. The Gantt Chart also contains important dates and deadlines, relevant to the project completion in the spring semester, such as progress reports, presentations, and proposal dates. The other tasks are the ones from the proposed tasks and do not need further elaboration.

FIGURE C.6– Gantt Chart of Project

Budget

FIGURE C.7 – List of Materials

Component

Quantity

Price

PIC16LF877 Processor

$1.59

SanDisk Multimedia Card

$24.99

Sanyo LCD

$7.00

VS1001K (Decoder, DAC & Amplifier)

$20.00

Other Parts

$25.00

TOTAL

$78.58

The cost of labor for constructing this portable MP3 player was approximated at $10,050. This was calculated by using the rate of $25/hr. The hours were divided into two different types. The first was school hours and the second was summer hours. The school hours were calculated by approximating 4 hours per person per week multiplied 26 school weeks resulting in 312 hours. Summer hours were estimated at 2 hours per week by each person multiplied by 15 weeks in the summer giving us roughly 90 hours. The sum of these two types of hours was approximately 402 hours. Therefore the total cost of labor with an overhead rate of 100% was $10,050.

Facilities and Resources

The majority of the work for this project will be completed at the facilities of Villanova University. Many electronic devices will be used and a static-free or low-static environment is necessary when handling such devices. The components for our project will be ordered from online retailers and will be shipped and handled by the university mailroom. After we receive the parts for the project, we will test the components in the labs in the Center for Engineering Education and Research (CEER) building. The laboratories in CEER provide access to experimental systems through control stations equipped with state-of-the-art modeling, design, analysis, and implementation software. Our team will gain access to the labs that will aid in our design, construction, and experimentation. Digital signal processing and telecommunications equipment will enable the testing of our system. The advanced electronics, microprocessor systems, audio, signal processing, controls, solid state devices, and digital systems design laboratories are required for the completion of this project.

The project personnel have relevant qualifications for working on their particular tasks of the project. Brian Allen has the programming knowledge that will be useful when working with the memory component. Zeeshan Khan has experience with digital signal processing courses that will aid him in the setup of the decoder chip. Jerry Koshy is familiar with graphical user interfaces and can handle the interface part of the MP3 player. All team members have programming experience for the PIC and circuit construction abilities.

References

1. http://help.mp3.com/help/category/aboutmp3s.html , MP3 Format Information.

2. http://www.ccs.neu.edu/home/bchafy/mp3.html#Players , Basic Component Scaling.

3. http://www.howstuffworks.com/hard-disk.htm , How different components work.

4. http://www.wdc.com/products/ , Western Design Hard Drive Data.

5. http://www.acercm.com/storage/storage_52x.html , Acer CD-ROM Data.

6. http://www.sandisk.com/tech/oem_design/mmc_dc.asp , MMC Information.

7. http://www.micronas.com/products/documentation/consumer/mas3507d/downloads/mas3507d_3pd.pdf , MAS

Decoder Data Sheet.

8. http://www.vlsi.fi/datasheets/vs1001.pdf , VS1001K Data Decoder sheet.

9. http://us.st.com/stonline/prodpres/dedicate/mp3/sta013.htm , STA013 Decoder Data Sheet.

10. http://www.atmel.com/atmel/acrobat/doc0838.pdf , Atmel Chip Data Sheet.